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<title>Sample Waveforms for FIFO_Data.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file FIFO_Data.vhd </CENTER></h2>
<P>The following waveforms show the behavior of dcfifo_mixed_widths megafunction for the chosen set of parameters in design FIFO_Data.vhd.  The design FIFO_Data.vhd has a write-side depth of 8192 words of 8 bits each. a read-side width of 4. The fifo is in legacy synchronous mode.  The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
<CENTER><img src=FIFO_Data_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions . </P>
<CENTER><img src=FIFO_Data_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
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